The present invention relates generally to semiconductor device processing and, more particularly, to a method and structure for improved alignment in Magnetic (or magneto-resistive) random access memory (MRAM) integration.
MRAM is a non-volatile random access memory technology that could replace the dynamic random access memory (DRAM) as the standard memory for computing devices. The use of MRAM as a non-volatile RAM would allow for “instant on” systems that come to life as soon as the system is turned on, thus saving the amount of time needed for a conventional PC, for example, to transfer boot data from a hard disk drive to volatile DRAM during system power up.
A magnetic memory element (also referred to as a tunneling magneto-resistive, or TMR device) includes a structure having ferromagnetic layers separated by an insulating non-magnetic layer (barrier), and arranged into a magnetic tunnel junction (MTJ). Digital information is stored and represented in the memory element as directions of magnetization vectors in the magnetic layers. More specifically, the magnetic moment of one magnetic layer (also referred to as a reference layer) is usually maintained in a preassigned direction, while the magnetic moment of the magnetic layer on the other side of the tunnel barrier (also referred to as a “free” layer) may be switched during operation between the same direction and the opposite direction with respect to the fixed magnetization direction of the reference layer. The orientations of the magnetic moment of the free layer adjacent to the tunnel junction are also known as “parallel” and “antiparallel” states, wherein a parallel state refers to the same magnetic alignment of the free and reference layers, while an antiparallel state refers to opposing magnetic alignments therebetween.
Depending upon the magnetic state of the free layer (parallel or antiparallel), the magnetic memory element exhibits two different resistance values in response to a voltage applied across the tunnel junction barrier. The particular resistance of the TMR device thus reflects the magnetization state of the free layer, wherein resistance is typically “low” when the magnetization is parallel, and “high” when the magnetization is antiparallel. Accordingly, a detection of changes in resistance allows a MRAM device to provide information stored in the magnetic memory element (i.e., a read operation). There are different methods for writing a MRAM cell; for example, a Stoner-Wohlfarth astroid MRAM cell is written to through the application of fields to exceed a critical curve or stability threshold, in order to magnetically align the free layer in a parallel or antiparallel state. The free layer is fabricated to have a preferred axis for the direction of magnetization called the “easy axis” (EA), and is typically set by a combination of intrinsic anisotropy, strain induced anisotropy, and shape anisotropy of the MTJ.
One type of existing MRAM device architecture is what is referred to as a field effect transistor (FET) based configuration. In the FET-based configuration, each MRAM cell includes a select transistor associated therewith, in addition to an MTJ. By keeping the select transistors to cells not being read in a non-conductive state, shunting current is prevented from flowing through neighboring devices. The tradeoff with the FET-based configuration versus a cross point cell (XPC)-based configuration (in which each cell is located at the crossing point between parallel conductive wordlines in one horizontal plane and perpendicularly running bit lines in another horizontal plane) is the area penalty associated with the location of the select transistors and additional metallization lines. In a conventionally formed FET-based MRAM device, the MTJ is typically formed over a conductive metal strap that laterally connects the bottom of the MTJ to the select FET (through a via, metallization line and contact area stud). A metal hardmask layer or via on the top of the MTJ is coupled to an upper metallization line.
One of the challenges in forming MRAM devices during Back End of Line (BEOL) processing of Complimentary Metal Oxide Semiconductor (CMOS) integration lies in the lithographic alignment of MTJs to the metal level beneath. In most conventional BEOL processing approaches, the dielectric films used are optically transparent, thereby allowing a stepper to view the alignment marks of the metallization level beneath for alignment thereto. However, since the MTJ metal stack is opaque, the alignment marks of the metal level beneath an MTJ stack are not visible.
One existing approach to alignment for MTJ stacks is to introduce topography into the alignment mark area of the underlying metal level that can be seen through the MTJ, such as taught in U.S. Pat. No. 6,858,441. However, the chemical mechanical polishing (CMP) prior to MTJ stack deposition that is associated with this technique can lead to dishing and trapped slurry residue, this making the alignment more difficult. In another approach (e.g., U.S. Pat. No. 6,933,204, assigned to the assignee of the present application), a portion of the opaque MTJ stack layer over a set of alignment marks is removed prior to hardmask patterning that is aligned to a lower metallization level. The marks are visible beneath an optically transparent layer once the portion of the opaque MTJ layer is removed.
However, subsequent to the initial tunnel junction lithographic alignment to the lower metal level, the resulting hardmask and metal strap etch processes can degrade the optically exposed alignment marks, which are only protected by a thin optically transparent layer (e.g., Ta/TaN). As a result, further alignment steps that also utilize the same alignment marks (e.g., aligning vias that directly connect an upper level metal line to a lower metal line) can become more difficult to perform. Accordingly, it would be desirable to be able to implement alignment of MTJ stacks in a manner that utilizes optically transparent alignment marks, but that also maintains the capability for additional alignment following etch processes subsequent to a first alignment.